Verilog

Verilog is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction. It is also used in the verification of analog circuits and mixed-signal circuits.

It can be used to write hardware code which is then synthesised into electronics on an FPGA (field programmable gate array) or ASIC (application specific integrated circuit).

SystemVerilog is the newest version of the Verilog HDL.

For queries about this topic, contact Ashley Setter.

Projects

Centre for Doctoral Training in Next Generation Computational Modelling

Hans Fangohr, Ian Hawke, Peter Horak (Investigators), Susanne Ufermann Fangohr, Thorsten Wittemeier, Kieran Selvon, Alvaro Perez-Diaz, David Lusher, Ashley Setter, Emanuele Zappia, Hossam Ragheb, Ryan Pepper, Stephen Gow, Jan Kamenik, Paul Chambers, Robert Entwistle, Rory Brown, Joshua Greenhalgh, James Harrison, Jonathon Waters, Ioannis Begleris, Craig Rafter

The £10million Centre for Doctoral Training was launched in November 2013 and is jointly funded by EPSRC, the University of Southampton, and its partners.

The NGCM brings together world-class simulation modelling research activities from across the University of Southampton and hosts a 4-year doctoral training programme that is the first of its kind in the UK.

Dynamics simulations for quantum feedback to steer a single-particle harmonic oscillator in non-classical states

Hendrik Ulbricht (Investigator), Ashley Setter

This PhD project is about using digital electronics to implement a parametric feedback loop to modulate the intensity of an optical trapping laser in order to stabilise/cool the centre of mass motion of a nanoparticle. It is then intended we use digital parametric feedback to drive the motion of the particle, which is essentially a quantum harmonic oscillator, into non-classical quantum states such as squeezed and number states.