| Abstract |
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| Instruction systolic arrays have been developed in order to combine the speed and simplicity of systolic arrays with the flexibility of MIMD parallel computer systems. Instruction systolic arrays are available as square arrays of small RISC processors capable of performing integer and floating point arithmetic. In this paper we show, that the systolic control flow can be used to an efficient implementation of arithmetic operations on long operands, e.g. 1024 bits. The demand for long operand arithmetic arises in the field of cryptography. It is shown how the new arithmetic leads to a high-speed implementation for RSA encryption and decryption. |
| Contact |
| Bertil Schmidt Lehrstuhl fur Informatik I=20,Ahornstra=DFe 55=20,D - 52074 Aachen,Germany bes@i1.informatik.rwth-aachen.de |