| Abstract |
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| In this paper, we present a methodology to improve hardwarecache utilization by program transformations so as to achieve lower power requirements for real-time multimedia applications. Our methodology is targeted towards embedded parallel multimedia and DSPprocessors. This methodology takes into account many program parameters like the locality of data, size of data structures, access structures of large array variables, regularity of loop nests and the size and type of cache with the objective of improving cache performance for lower power. Experiments on real life demonstrators illustrate thefact that our methodology is able to achieve significant gain in powerrequirements while meeting all other system constraints. We also present some results about software controlled caches and give a comparison between both the types of caches and an insight about where the largest gains lie. |
| Contact |
| Chidamber Kulkarni IMEC-VSDM,Kapeldreef 75,,B-3001, Leuven,Belgium kulkarni@imec.be |