Self Timed ASRAM

Here the Self-timed asynchronous SRAM chip is tested, together with a hybrid SCC-CBB capacitor-based power delivery system (HCBB). Unlike synchronous memory, whose clock needs to be adjusted according to the worst case scenario when operating under adverse conditions (power, Vdd, variability, etc.), the self-timed ASRAM automatically adjusts its speed according to the Vdd. It becomes slower with reducing Vdd, when the voltage is further reduced to some very low value, the ASRAM will simply stop, presenting a "stuck at" behaviour to the environment. It does maintain data retention for some range of Vdd after it has stopped. If the Vdd is raise again afterwards, the ASRAM will simply resume operation without losing the data stored. The HCBB proved to be an ideal power source for discovering the ASRAM's behaviour by providing a variety of Vdd scenarios.



For more information, please contact Prof Alex Yakovlev, Newcastle University.