The UK Research Programme concerned with developing SiGe MOS technologies.
Funded pricipally by the EPSRC, 13 research teams from 9 UK universities work together on the programme along with industrial partners Avant!, Daimler- Chrysler, Infineon Technologies and Zarlink Semiconductor.
The project is concerned with the integration of strained silicon and silicon germanium layers in decananometre CMOS processes, with both conventional doped polysilicon gate and metal replacement gate processes. Work is also focused on limited area growth SiGe for virtual substrate strained silicon devices and the integration of a high-k gate dielectric into a SiGe MOS process.