The International Technology Roadmap for semiconductors has identified a new gate stack and material as one of the grand challenges for the coming years. The thickness of the incumbent SiO2 gate oxide has been scaled down to less than 2 nm, and further reduction is impossible because of the leakage currents due to direct tunneling. For this reason, the present gate oxide dielectric materials will eventually be replaced by a high-k dielectric gate oxide. The current proposal aims at identifying promising materials for CMOS gate high-k dielectrics by using combinatorial methods for synthesis and screening of materials in a collaboration between the departments of Electronics & Computer Science and Chemistry of the University of Southampton. Unlike industrial methods such as atomic layer chemical vapour deposition, our multiple e-beam deposition will allow us to vary the concentration and thickness of the gate oxide on the same wafer. Not only will this enable identification of the most promising materials, it will also show systematic correlation between chemical and structural properties on one side and electrical properties on the other side over a wide range of concentrations and elements. This makes it feasible to detect patterns in the correlation which will lead to a much better physical understanding of the factors influencing the electrical properties of the gate dielectric in CMOS transistors.