ECS Intranet:
Monolithic Active Pixel Arrays

A visible wavelength linear photosensor featuring a pixel size of 3 mm has been designed for fabrication using commercial 0.25 mm CMOS technology. For the photo-sensing element, the design uses a special deep N-well in P-epi diode offered by the foundry for imaging devices. Pixel reset is via an adjacent p-FET, thus allowing high reset voltages for a wide pixel voltage swing. The pixel voltage is buffered using a voltage-follower op-amp and a sampling scheme is used to allow correlated double sampling (CDS) for removal of reset noise. Reset and signal levels are buffered through a 16:1 multiplexer to a switched capacitor amplifier which performs the CDS function. Incorporated in the CDS circuit is a programmable gain of 1:8 for increased signal-to-noise ratio at low signal levels. Data output is via 4 analogue output drivers for off-chip conversion. Each driver supplies a differential output voltage with a 71V swing for improved power supply noise rejection. The readout circuitry is designed for 12 bit accuracy at frame rates of up to 6.25 kHz. This gives a peak data rate at each output driver of 10M samples/s. The device will operate on a 3.3V supply and will dissipate approximately 950mW. Simulations indicate an equivalent noise charge at the pixel of 66.3 for a full well capacity of 255,000, giving a dynamic range of 71.7 dB.

Partners

• N.R. Waltham, Rutherford Appleton

Funding

Principal Investigators

• [hidden]
• Professor Bashir M Al-Hashimi

Other Investigators

• qrm01r