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Highly-parallel algorithms and architectures for high-throughput wireless receivers

During the past two decades, reliable wireless communication at near-theoretical-limit transmission throughputs has been facilitated by receivers that operate on the basis of the Bahl-Cocke-Jelinek-Raviv (BCJR) algorithm. Most famously, this algorithm is employed for turbo error correction in the Long Term Evolution (LTE) standard for cellular telephony, as well as in its previous-generation predecessors. However, the transmission throughput of these standards is limited by the processing throughput of the turbo decoder. This limit may be attributed to the data dependencies of the BCJR algorithm, resulting in an inherently serial nature that cannot be readily mapped to processing architectures having a high degree of parallelism. Against this background, this project will redesign turbo decoder implementations at an algorithmic level, rather than only at the architectural level, which is the State-Of-the-Art (SOA) approach. More specifically, we have devised an alternative to the BCJR algorithm, which has the same error correction capability, but does not have any data dependencies. Owing to this, our algorithm can be mapped to highly-parallel many-core processing architectures, facilitating an LTE turbo decoder processing throughput that is several times higher than the SOA, satisfying future demands for gigabit throughputs. In collaboration with ARM, Altera and BT, this research addresses key EPSRC priorities in the Information and Communication Technologies theme, including 'Many-core architectures and concurrency in distributed and embedded systems' and 'Towards an intelligent information infrastructure'.

Relevant Links

• EPSRC grant EP/L010550/1

Partners

• Altera
• ARM
• BT

Funding

• EPSRC EP/L010550/1

Principal Investigators

• Robert G Maunder

Other Investigators

• Professor Lajos Hanzo
• Professor Bashir M Al-Hashimi