| Skip to main content | Skip to sub navigation |

This is now an inactive research group it's members have moved on. You can find them at their new research groups:

ECS Intranet:
ESD Seminars


Date Time Location Speaker Topic
23/02/2011 13:00-13:25

Seminar Room 1 (59/1257)

Jatin Mistry Sub-Clock Power-Gating Technique for Minimising Leakage Power During Active Mode

Abstract:This paper presents a new technique, called sub-clock power gating, for reducing leakage power in digital circuits. The proposed technique works concurrently with voltage and frequency scaling and  power reduction is achieved by power gating within the clock cycle during active mode unlike traditional power gating which is applied during idle mode. The proposed technique can be  implemented using standard EDA tools with simple modifications to the standard power gating design flow. Using a 90nm technology library, the technique is validated using two case studies: 16-bit  parallel multiplier and ARM Cortex-M0 microprocessor, provided by our industrial project partner. Compared to designs without sub-clock power gating, in a given power budget, we show that leakage power saved allows 45x and 2.5x improvements in energy efficiency in the case of multiplier and microprocessor, respectively.

 

 
Date Time Location Speaker Topic
23/2/2010 13:30-13:55

Seminar Room 1 (59/1257)

Phil (Leran) Wang

An extension to SystemC-A to support mixed-technology systems with distributed components

 Abstract:  This contribution proposes syntax extensions to SystemC-A that support mixed-technology system modelling where components might exhibit distributed behaviour modelled by partial differential equations. The important need for such extensions arises from the well known modelling difficulties in hardware description languages where complex electronics in a mixed-technology system interfaces with distributed components from different physical domains, e.g. mechanical, magnetic or thermal. A digital MEMS accelerometer with distributed mechanical sensing element is used as a case study to illustrate modelling capabilities offered by the proposed extended syntax of SystemC-A.

 
Date Time Location Speaker Topic
tba 13:00-13:50 tba tba tba
Abstract