NIRGAM
A Simulator for NoC Interconnect Routing and Application Modeling

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NoC Struct Reference

Represents the entire Network-on-Chip. More...

#include <NoC.h>

Inheritance diagram for NoC:

List of all members.

Public Member Functions
	SC_HAS_PROCESS (NoC)
	Constructor.
	NoC (sc_module_name NoC, int num_rows, int num_cols)
void	entry ()
	Keeps count of number of simulation cycles.
Public Attributes
sc_in< bool >	switch_cntrl
	Clock input port.
int	rows
	number of rows in topology
int	cols
	number of columns in topology
BaseNWTile *	nwtile [MAX_NUM_ROWS][MAX_NUM_COLS]
	A 2-d array of network tiles.
signals	sigs [MAX_NUM_ROWS][MAX_NUM_COLS]
	Signals to interconnect network tiles.

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Detailed Description

Represents the entire Network-on-Chip.

This module represents the NoC. It implements an array of network tiles and connectivity among them.

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Constructor & Destructor Documentation

NoC::NoC (  sc_module_name  NoC, int  num_rows, int  num_cols )

Constructor to generate topology. It creates 2-d toroidal or non- toroidal mesh of m x n network tiles depending on input from user. Parameters: number of rows in topology number of columns in topology The constructor implements the following: interconnect network tiles assign tile IDs connect clock signal to clock input port of tiles.

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Member Function Documentation

void NoC::entry (   )

Keeps count of number of simulation cycles. This thread keeps track of global simulation count. It also closes logfiles upon completion of simulation.

NoC::SC_HAS_PROCESS (  NoC   )

Constructor.

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Member Data Documentation

int NoC::cols

number of columns in topology

BaseNWTile* NoC::nwtile[MAX_NUM_ROWS][MAX_NUM_COLS]

A 2-d array of network tiles.

int NoC::rows

number of rows in topology

signals NoC::sigs[MAX_NUM_ROWS][MAX_NUM_COLS]

Signals to interconnect network tiles.

sc_in<bool> NoC::switch_cntrl

Clock input port.

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