NIRGAM
A Simulator for NoC Interconnect Routing and Application Modeling

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OutputChannel< num_ip > Struct Template Reference

Module to represent an Output Channel. More...

#include <OutputChannel.h>

Inheritance diagram for OutputChannel< num_ip >:

List of all members.

Public Member Functions
	SC_CTOR (OutputChannel)
	Constructor.
void	entry ()
	reads and processes incoming flit
void	closeLogs ()
void	setTileID (UI tileID, UI portN, UI portS, UI portE, UI portW)
	sets tile ID and id corresponding to port directions
Public Attributes
sc_in< flit >	inport [num_ip]
	input data/flit ports (one for each IC)
sc_out< bool >	inReady [num_ip]
	output port to send ready signal to IC
sc_in< bool >	switch_cntrl
	clock input port
sc_out< flit >	outport
	output data/flit port
sc_in< creditLine >	credit_in [NUM_VCS]
	input port to recieve credit info (buffer status) from ICs of neighbor tiles
UI	tileID
	unique tile ID
UI	cntrlID
	control ID to identify channel direction (N, S, E, W, C)
UI	portN
	port number representing North direction
UI	portS
	port number representing South direction
UI	portE
	port number representing East direction
UI	portW
	port number representing West direction
switch_reg	r_in [num_ip]
	registers to store flit from inport, one for each inport
switch_reg	r_vc [NUM_VCS]
	registers, one for each next VCID
ULL	latency
	total latency
ULL	num_pkts
	total number of packets
ULL	num_flits
	total number of flits
ULL	input_time
	generation timestamp of head flit of a packet
float	avg_latency
	average latency (in clock cycles) per packet
float	avg_latency_flit
	average latency (in clock cycles) per flit
float	avg_throughput
	average throughput (in Gbps)
int	beg_cycle
	clock cycle in which first flit is recieved in the channel
int	end_cycle
	clock cycle in which last flit leaves the channel
int	total_cycles
	total number of clock cycles

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Detailed Description

template<UI num_ip = NUM_IC>
struct OutputChannel< num_ip >

Module to represent an Output Channel.

This module defines an Output Channel in a network tile

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Member Function Documentation

template<UI num_ip> void OutputChannel< num_ip >::closeLogs (   )

closes logfiles at the end of simulation and computes performance stats

template<UI num_ip> void OutputChannel< num_ip >::entry (   )

reads and processes incoming flit Process sensitive to inport event and clock event clock event: send flit from register r_vc to output port move any waiting flits from register r_in to r_vc inport event: read flit from inport and store in register r_in

template<UI num_ip = NUM_IC> OutputChannel< num_ip >::SC_CTOR (  OutputChannel< num_ip >   )

Constructor.

template<UI num_ip> void OutputChannel< num_ip >::setTileID (  UI  id, UI  port_N, UI  port_S, UI  port_E, UI  port_W )

sets tile ID and id corresponding to port directions Method to assign tile IDs and port IDs

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Member Data Documentation

template<UI num_ip = NUM_IC> float OutputChannel< num_ip >::avg_latency

average latency (in clock cycles) per packet

template<UI num_ip = NUM_IC> float OutputChannel< num_ip >::avg_latency_flit

average latency (in clock cycles) per flit

template<UI num_ip = NUM_IC> float OutputChannel< num_ip >::avg_throughput

average throughput (in Gbps)

template<UI num_ip = NUM_IC> int OutputChannel< num_ip >::beg_cycle

clock cycle in which first flit is recieved in the channel

template<UI num_ip = NUM_IC> UI OutputChannel< num_ip >::cntrlID

control ID to identify channel direction (N, S, E, W, C)

template<UI num_ip = NUM_IC> sc_in<creditLine> OutputChannel< num_ip >::credit_in[NUM_VCS]

input port to recieve credit info (buffer status) from ICs of neighbor tiles

template<UI num_ip = NUM_IC> int OutputChannel< num_ip >::end_cycle

clock cycle in which last flit leaves the channel

template<UI num_ip = NUM_IC> sc_in<flit> OutputChannel< num_ip >::inport[num_ip]

input data/flit ports (one for each IC)

template<UI num_ip = NUM_IC> ULL OutputChannel< num_ip >::input_time

generation timestamp of head flit of a packet

template<UI num_ip = NUM_IC> sc_out<bool> OutputChannel< num_ip >::inReady[num_ip]

output port to send ready signal to IC

template<UI num_ip = NUM_IC> ULL OutputChannel< num_ip >::latency

total latency

template<UI num_ip = NUM_IC> ULL OutputChannel< num_ip >::num_flits

total number of flits

template<UI num_ip = NUM_IC> ULL OutputChannel< num_ip >::num_pkts

total number of packets

template<UI num_ip = NUM_IC> sc_out<flit> OutputChannel< num_ip >::outport

output data/flit port

template<UI num_ip = NUM_IC> UI OutputChannel< num_ip >::portE

port number representing East direction

template<UI num_ip = NUM_IC> UI OutputChannel< num_ip >::portN

port number representing North direction

template<UI num_ip = NUM_IC> UI OutputChannel< num_ip >::portS

port number representing South direction

template<UI num_ip = NUM_IC> UI OutputChannel< num_ip >::portW

port number representing West direction

template<UI num_ip = NUM_IC> switch_reg OutputChannel< num_ip >::r_in[num_ip]

registers to store flit from inport, one for each inport

template<UI num_ip = NUM_IC> switch_reg OutputChannel< num_ip >::r_vc[NUM_VCS]

registers, one for each next VCID

template<UI num_ip = NUM_IC> sc_in<bool> OutputChannel< num_ip >::switch_cntrl

clock input port

template<UI num_ip = NUM_IC> UI OutputChannel< num_ip >::tileID

unique tile ID

template<UI num_ip = NUM_IC> int OutputChannel< num_ip >::total_cycles

total number of clock cycles

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