Low Density Parity Check (LDPC) error correction codes have found application in numerous standards for both wired and wireless communication, including those for home networking, Local Area Networking (LAN), cellular systems, wireless LAN and Digital Video Broadcasting (DVB). LDPC codes enjoy near-optimal error correction performance, which facilitates communication throughputs that approach the capacity of the channel and meet the ever-increasing consumer demand for high-speed data. However, in order to realise these high communication throughputs, the LDPC encoder and decoder must have correspondingly-high processing throughputs. In order to facilitate the rapid prototyping of high-speed communication systems, there is a need for Field Programmable Gate Array (FPGA) realisations of LDPC decoders having high processing throughputs. While a throughput of 16.2 Gbps has already been achieved by the current state-of-the-art design, this is achieved by employing a fully-parallel architecture, which supports only a single LDPC matrix. Indeed, many more high-throughput FPGA LDPC architectures have been proposed in the literature, but each has its own drawbacks. These drawbacks may be manifested as relatively poor error correction performance, resource usage, energy consumption, latency, reconfigurability or LDPC matrix dimensions, for example. Hence, there is a need for generalised high-throughput FPGA architectures that can be configured to support not only various different LDPC matrices, but also various different trade-offs between the contradictory system characteristics listed above. Furthermore, there is a need for methodologies that allow the configuration of these architectures to be holistically designed, in order to readily achieve an appropriate trade-off between the characteristics. In this way, the resultant general purpose architectures would have significantly more applicability and commercial viability than existing high-throughput architectures.