NIRGAM
A Simulator for NoC Interconnect Routing and Application Modeling

Home | Download | Documentation | People | Support

InputChannel< num_op > Struct Template Reference

Module to represent an Input Channel. More...

#include <InputChannel.h>

Inheritance diagram for InputChannel< num_op >:

List of all members.

Public Member Functions
	SC_CTOR (InputChannel)
	Constructor.
void	read_flit ()
	reads flit from i/p port and calls function to store it in buffer
void	store_flit_VC (flit *)
	stores flit in buffer
void	route_flit ()
	routes the flit at the front of fifo buffer
void	routing_src (flit *)
	routing function for algorithms containing entire path in header (source routing)
void	routing_dst (flit *)
	routing function for algorithms containing destination address in header
void	transmit_flit ()
void	setTileID (UI tileID, UI portN, UI portS, UI portE, UI portW)
	sets tile ID and id corresponding to port directions
void	resetCounts ()
	resets buffer counts to zero
void	closeLogs ()
	closes logfiles
int	reverse_route (int)
	reverses route (to be used in future)
Public Attributes
sc_in< bool >	switch_cntrl
	input clock port
sc_in< flit >	inport
	input data/flit port
sc_out< flit >	outport [num_op]
	ouput data/flit ports (one for each output channel)
sc_in< bool >	outReady [num_op]
	input ports for ready signal from OCs
sc_out< bool >	vcRequest
	output port for sending request to VCA
sc_in< bool >	vcReady
	input port for ready signal from VCA
sc_out< sc_uint< 2 > >	opRequest
	output port for sending OC requested to VCA
sc_in< sc_uint< VCS_BITSIZE+1 > >	nextVCID
	input port to recieve next VCID from VCA
sc_out< creditLine >	credit_out [NUM_VCS]
	output ports to send credit info (buffer status) to OC, VCA and Ctr
sc_out< request_type >	rtRequest
	output port to send request to Controller
sc_in< bool >	rtReady
	input port to recieve ready signal from Controller
sc_out< sc_uint< ADDR_SIZE > >	destRequest
	output port to send destination address to Controller
sc_out< sc_uint< ADDR_SIZE > >	sourceAddress
	output port to send source address to Controller
sc_in< sc_uint< 3 > >	nextRt
	input port to recieve routing decision (next hop) from Controller
VC	vc [NUM_VCS]
	Virtual channels.
UI	cntrlID
	Control ID to identify channel direction.
UI	tileID
	Tile ID.
UI	portN
	port number representing North output direction
UI	portS
	port number representing South output direction
UI	portE
	port number representing East output direction
UI	portW
	port number representing West output direction
UI	numBufReads
	number of buffer reads in the channel
UI	numBufWrites
	number of buffer writes in the channel
UI	numBufsOcc
	number of occupied buffers
UI	numVCOcc
	number of occupied virtual channels
ULL	sim_count
	keeps track of number of clock cycles

---

Detailed Description

template<UI num_op = NUM_OC>
struct InputChannel< num_op >

Module to represent an Input Channel.

This module defines an Input Channel in a network tile

---

Member Function Documentation

template<UI num_op> void InputChannel< num_op >::closeLogs (   )

closes logfiles Method to close logfiles

template<UI num_op> void InputChannel< num_op >::read_flit (   )

reads flit from i/p port and calls function to store it in buffer Process sensitive to inport event Reads flit from input port and calls function to store in buffer

template<UI num_op> void InputChannel< num_op >::resetCounts (   )

resets buffer counts to zero Method to resut buffer stats to zero

template<UI num_op> int InputChannel< num_op >::reverse_route (  int   )

reverses route (to be used in future)

template<UI num_op> void InputChannel< num_op >::route_flit (   )

routes the flit at the front of fifo buffer Process sensitive to clock Calls routing functions if head/hdt flit at the front of fifo

template<UI num_op> void InputChannel< num_op >::routing_dst (  flit *  flit_in  )

routing function for algorithms containing destination address in header Method to call controller for routing algorithms that require destination address

template<UI num_op> void InputChannel< num_op >::routing_src (  flit *  flit_in  )

routing function for algorithms containing entire path in header (source routing) Method to call Controller for source routing

template<UI num_op = NUM_OC> InputChannel< num_op >::SC_CTOR (  InputChannel< num_op >   )

Constructor.

template<UI num_op> void InputChannel< num_op >::setTileID (  UI  id, UI  port_N, UI  port_S, UI  port_E, UI  port_W )

sets tile ID and id corresponding to port directions Method to assign tile IDs and port IDs

template<UI num_op> void InputChannel< num_op >::store_flit_VC (  flit *  flit_in  )

stores flit in buffer Method to store flit in fifo buffer

template<UI num_op> void InputChannel< num_op >::transmit_flit (   )

transmits flit at the front of fifo to output port

---

Member Data Documentation

template<UI num_op = NUM_OC> UI InputChannel< num_op >::cntrlID

Control ID to identify channel direction.

template<UI num_op = NUM_OC> sc_out<creditLine> InputChannel< num_op >::credit_out[NUM_VCS]

output ports to send credit info (buffer status) to OC, VCA and Ctr

template<UI num_op = NUM_OC> sc_out<sc_uint<ADDR_SIZE> > InputChannel< num_op >::destRequest

output port to send destination address to Controller

template<UI num_op = NUM_OC> sc_in<flit> InputChannel< num_op >::inport

input data/flit port

template<UI num_op = NUM_OC> sc_in<sc_uint<3> > InputChannel< num_op >::nextRt

input port to recieve routing decision (next hop) from Controller

template<UI num_op = NUM_OC> sc_in<sc_uint<VCS_BITSIZE+1> > InputChannel< num_op >::nextVCID

input port to recieve next VCID from VCA

template<UI num_op = NUM_OC> UI InputChannel< num_op >::numBufReads

number of buffer reads in the channel

template<UI num_op = NUM_OC> UI InputChannel< num_op >::numBufsOcc

number of occupied buffers

template<UI num_op = NUM_OC> UI InputChannel< num_op >::numBufWrites

number of buffer writes in the channel

template<UI num_op = NUM_OC> UI InputChannel< num_op >::numVCOcc

number of occupied virtual channels

template<UI num_op = NUM_OC> sc_out<sc_uint<2> > InputChannel< num_op >::opRequest

output port for sending OC requested to VCA

template<UI num_op = NUM_OC> sc_out<flit> InputChannel< num_op >::outport[num_op]

ouput data/flit ports (one for each output channel)

template<UI num_op = NUM_OC> sc_in<bool> InputChannel< num_op >::outReady[num_op]

input ports for ready signal from OCs

template<UI num_op = NUM_OC> UI InputChannel< num_op >::portE

port number representing East output direction

template<UI num_op = NUM_OC> UI InputChannel< num_op >::portN

port number representing North output direction

template<UI num_op = NUM_OC> UI InputChannel< num_op >::portS

port number representing South output direction

template<UI num_op = NUM_OC> UI InputChannel< num_op >::portW

port number representing West output direction

template<UI num_op = NUM_OC> sc_in<bool> InputChannel< num_op >::rtReady

input port to recieve ready signal from Controller

template<UI num_op = NUM_OC> sc_out<request_type> InputChannel< num_op >::rtRequest

output port to send request to Controller

template<UI num_op = NUM_OC> ULL InputChannel< num_op >::sim_count

keeps track of number of clock cycles

template<UI num_op = NUM_OC> sc_out<sc_uint<ADDR_SIZE> > InputChannel< num_op >::sourceAddress

output port to send source address to Controller

template<UI num_op = NUM_OC> sc_in<bool> InputChannel< num_op >::switch_cntrl

input clock port

template<UI num_op = NUM_OC> UI InputChannel< num_op >::tileID

Tile ID.

template<UI num_op = NUM_OC> VC InputChannel< num_op >::vc[NUM_VCS]

Virtual channels.

template<UI num_op = NUM_OC> sc_in<bool> InputChannel< num_op >::vcReady

input port for ready signal from VCA

template<UI num_op = NUM_OC> sc_out<bool> InputChannel< num_op >::vcRequest

output port for sending request to VCA

---