In this work, we showed that sleep transistor (ST) aging presents noticeable beneficial effects on static power and ST switch efficiency, whose magnitudes depend on operating conditions (Figure 1). The beneficial effect on static power has been proven also by means of experimental measurements (Figure 2). Based on this feature, we proposed a new ST design strategy (Figure 3) for reliable power gating, which offers better cost-reliability tradeoffs compared to alternative approaches based on either ST oversize, or adaptive body bias. Through HSPICE simulations, we showed a lifetime (thus long-term reliability) improvement up to 21.4x and average static power reduction up to 16.3% compared to a standard ST design approach, with no additional area overhead (Figure 4). Moreover, if a maximum target lifetime of either 5 or 10 years is considered, our proposed ST design strategy enables either to improve circuit operating frequency up to 9.9%, or to reduce ST area overhead up to 19.8%.
D. Rossi; V. Tenentes; S. Yang; S. Khursheed; B. M. Al-Hashimi, "Reliable Power Gating With NBTI Aging Benefits," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems , vol.PP, no.99, pp.1-10 (doi: 10.1109/TVLSI.2016.2519385)
D. Rossi, V. Tenentes, S. Khursheed and B. M. Al-Hashimi, "NBTI and leakage aware sleep transistor design for reliable and energy efficient power gating," 2015 20th IEEE European Test Symposium (ETS), Cluj-Napoca, 2015, pp. 1-6. (doi: 10.1109/ETS.2015.7138752)