Power management is an essential enabling technology in today's and future's low-power devices. The downside of power management is that it decreases the reliability and increase the testability cost of energy-efficient hardware as demonstrated by recent academic and industrial research including that reported by the investigation team. Currently, there are no fault models or test methods for power distribution networks and power management circuitry and no on-line soft error monitoring and correction methods for power management hardware. This project was focused on developing new fault models, methods, circuits and their validation to quantify and improve the resilience and testability of energy-efficient digital hardware. Particular emphasis was placed upon cost-effectiveness through joint consideration of reliability, and test and re-using on-chip hardware to minimise silicon area, power consumption and impact on functional performance.
The reliability analysis for this research was performed using a high-k 32 nm CMOS technology library. Software tools for integrating the developed techniques with ASIC design flow have been developed. The characterisation was conducted at both RT-Level and SPICE level and measurements were collected from a custom ARM research chip (TOKASHI).
The main outcomes of this project are:
- We demonstrated analytically and experimentally that static power consumption of VLSI designs decreases over time with Bias Temperature Instability (BTI) aging.
- We also demonstrated analytically and experimentally that leakage power reduction techniques become more efficient with Bias BTI aging.
- We proposed a sleep transistor design strategy for reliable power gating, in order to harvest the benefits offered by Negative Bias Temperature Instability (NBTI) aging.
- We also explored dynamic schemes of DVFS drowsy cache memory design in order to harvest BTI aging benefits for such memories.
- In addition, we researched a novel design-for-testability architecture for testing sleep transistors against stuck-open faults by considering a distributed model for the on-chip power network.
- We developed also a diagnosis algorithm for grading the impact of stuck-open faults on power gating designs when a distributed model for the on-chip power network is considered.
- Furthermore, we proposed a novel low cost coarse-grained sensor for BTI by exploiting the impact of BTI on leakage current and by reusing power gating DFT infrastructure
- Finally, a comprehensive evaluation was conducted on the effects of BTI on level shifters
Additional outcomes and ongoing pieces of this project are:
- A selective fault tolerance design technique by utilizing probabilistic fault models was developed
- A BTI-aware thermal management technique for DVFS designs using a fine-grained stress and temperature aware simulation flow (SPICE and RT-Level models characterization). The framework considers statistical probable workload for computing devices stress and temperature depending on the system policies that are followed for dynamic thermal management.
http://eprints.soton.ac.uk/399868/ (best paper award nominee at Defect and Fault Tolerance in VLSI and Nanotechnology Systems Symposium (DFT'16), Connecticut, US)
- A novel resistive based fault model for power networks and for characterizing the power gating designs in terms of power reduction efficiency.
Please consider the publications of the project for more detail.