NIRGAM
A Simulator for NoC Interconnect Routing and Application Modeling

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NWTile< num_nb, num_ic, num_oc > Struct Template Reference

Module to represent a tile in NoC. More...

#include <NWTile.h>

Inheritance diagram for NWTile< num_nb, num_ic, num_oc >:

List of all members.

Public Member Functions
	SC_HAS_PROCESS (NWTile)
	Constructor.
	NWTile (sc_module_name NWTile, UI tileID)
void	entry ()
	Writes buffer utilization information at the tile, at each clock cycle.
void	setID (UI)
	sets unique tile id and associates ports with directions
void	closeLogs ()
	closes log files at the end of simulation
float	return_latency (int port_dir)
	returns average latency per packet for a channel
float	return_latency_flit (int port_dir)
	returns average latency per flit for a channel
float	return_avg_tput (int port_dir)
	returns average throughput for a channel
int	return_total_latency ()
	returns total latency across all channels in the tile
int	return_total_flits ()
	returns total flits across all channels in the tile
int	getportid (int port_dir)
	returns id corresponding to a port direction (N, S, E, W)
	SC_HAS_PROCESS (BaseNWTile)
Public Attributes
sc_in< bool >	switch_cntrl
	input clock port
sc_in< flit >	ip_port [num_nb]
	input data/flit ports
sc_out< flit >	op_port [num_nb]
	output data/flit ports
sc_in< creditLine >	credit_in [num_nb][NUM_VCS]
	input ports for credit line (buffer status)
sc_out< creditLine >	credit_out [num_nb][NUM_VCS]
	output ports for credit line (buffer status)
InputChannel< num_oc > *	Ichannel [num_ic]
	Input channels.
OutputChannel< num_ic > *	Ochannel [num_oc]
	Output channels.
VCAllocator< num_ic >	vcAlloc
	Virtual Channel Allocator.
ipcore *	ip
	IP Core.
Controller< num_ic >	ctr
	Controller.
sc_signal< flit >	flit_sig [num_ic][num_oc]
	signals to connect data outport of ICs to the data inport of the OCs
sc_signal< flit >	flit_CS_IC
	data line from ipcore to input channel
sc_signal< flit >	flit_OC_CR
	data line from output channel to ipcore
sc_signal< bool >	rdy [num_ic][num_oc]
	ready signals from ICs to OCs of neighboring tiles
sc_signal< bool >	vcReq [num_ic]
	Request signal for virtual channel allocation from IC to VCA.
sc_signal< sc_uint< 2 > >	opReq [num_ic]
	Output port requested from IC to VCA.
sc_signal< bool >	vcReady [num_ic]
	Ready signal from VCA to IC.
sc_signal< sc_uint< VCS_BITSIZE+1 > >	nextvc [num_ic]
	Virtual channel id allocated from VCA to IC.
sc_signal< creditLine >	creditIC_CS [NUM_VCS]
	credit line from core channel to VCA and ipcore
sc_signal< request_type >	rtReq [num_ic]
	Routing request signal from IC to Ctr.
sc_signal< sc_uint< ADDR_SIZE > >	destReq [num_ic]
	Destination address from IC to Ctr.
sc_signal< sc_uint< ADDR_SIZE > >	srcAddr [num_ic]
	Source address from IC to Ctr.
sc_signal< bool >	rtReady [num_ic]
	Ready signal from Ctr to IC.
sc_signal< sc_uint< 3 > >	nextRt [num_ic]
	Route (output port) signal from Ctr to IC.
UI	tileID
	unique tile id
UI	portN
	port representing North direction
UI	portS
	port representing South direction
UI	portE
	port representing East direction
UI	portW
	port representing West direction

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Detailed Description

template<int num_nb = NUM_NB, int num_ic = NUM_IC, int num_oc = NUM_OC>
struct NWTile< num_nb, num_ic, num_oc >

Module to represent a tile in NoC.

This module defines a network tile and submodules within it. It is derived from abstract class BaseNWTile. Template parameters:

• num_nb: Number of neighbors
• num_ic: Number of input channels
• num_oc: Number of output channels

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Constructor & Destructor Documentation

template<int num_nb, int num_ic, int num_oc> NWTile< num_nb, num_ic, num_oc >::NWTile (  sc_module_name  NWTile, UI  id )

Constructor to create a network tile. Creates and connects the following submodules: Input Channels Output Channels Virtual Channel Allocator IP Core Controller Template parameters: num_nb: Number of neighbors num_ic: Number of input channels num_oc: Number of output channels Parameters to constructor: module name unique tile ID

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Member Function Documentation

template<int num_nb, int num_ic, int num_oc> void NWTile< num_nb, num_ic, num_oc >::closeLogs (   )

closes log files at the end of simulation Closes log files at the end of simulation

template<int num_nb, int num_ic, int num_oc> void NWTile< num_nb, num_ic, num_oc >::entry (   )

Writes buffer utilization information at the tile, at each clock cycle. Process sensitive to clock. Writes buffer utilization info at each clock

template<int num_nb, int num_ic, int num_oc> int NWTile< num_nb, num_ic, num_oc >::getportid (  int  port_dir  )

returns id corresponding to a port direction (N, S, E, W) Returns id corresponding to a given port direction (N, S, E, W)

template<int num_nb, int num_ic, int num_oc> float NWTile< num_nb, num_ic, num_oc >::return_avg_tput (  int  port_dir  )  [virtual]

returns average throughput for a channel Returns average throughput across a given channel Implements BaseNWTile.

template<int num_nb, int num_ic, int num_oc> float NWTile< num_nb, num_ic, num_oc >::return_latency (  int  port_dir  )  [virtual]

returns average latency per packet for a channel Returns average latency per packet across a given channel Implements BaseNWTile.

template<int num_nb, int num_ic, int num_oc> float NWTile< num_nb, num_ic, num_oc >::return_latency_flit (  int  port_dir  )  [virtual]

returns average latency per flit for a channel Returns average latency per flit across a given channel Implements BaseNWTile.

template<int num_nb, int num_ic, int num_oc> int NWTile< num_nb, num_ic, num_oc >::return_total_flits (   )  [virtual]

returns total flits across all channels in the tile Returns total number of flits across all channels in the tile Implements BaseNWTile.

template<int num_nb, int num_ic, int num_oc> int NWTile< num_nb, num_ic, num_oc >::return_total_latency (   )  [virtual]

returns total latency across all channels in the tile Returns total latency across all channels in the tile Implements BaseNWTile.

BaseNWTile::SC_HAS_PROCESS (  BaseNWTile   )  [inherited]

systemC constructor parameters - module name, tile id.

template<int num_nb = NUM_NB, int num_ic = NUM_IC, int num_oc = NUM_OC> NWTile< num_nb, num_ic, num_oc >::SC_HAS_PROCESS (  NWTile< num_nb, num_ic, num_oc >   )

Constructor.

template<int num_nb, int num_ic, int num_oc> void NWTile< num_nb, num_ic, num_oc >::setID (  UI  id  )

sets unique tile id and associates ports with directions set unique tile ID map port number to port direction

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Member Data Documentation

template<int num_nb = NUM_NB, int num_ic = NUM_IC, int num_oc = NUM_OC> sc_in<creditLine> NWTile< num_nb, num_ic, num_oc >::credit_in[num_nb][NUM_VCS]

input ports for credit line (buffer status)

template<int num_nb = NUM_NB, int num_ic = NUM_IC, int num_oc = NUM_OC> sc_out<creditLine> NWTile< num_nb, num_ic, num_oc >::credit_out[num_nb][NUM_VCS]

output ports for credit line (buffer status)

template<int num_nb = NUM_NB, int num_ic = NUM_IC, int num_oc = NUM_OC> sc_signal<creditLine> NWTile< num_nb, num_ic, num_oc >::creditIC_CS[NUM_VCS]

credit line from core channel to VCA and ipcore

template<int num_nb = NUM_NB, int num_ic = NUM_IC, int num_oc = NUM_OC> Controller<num_ic> NWTile< num_nb, num_ic, num_oc >::ctr

Controller.

template<int num_nb = NUM_NB, int num_ic = NUM_IC, int num_oc = NUM_OC> sc_signal<sc_uint<ADDR_SIZE> > NWTile< num_nb, num_ic, num_oc >::destReq[num_ic]

Destination address from IC to Ctr.

template<int num_nb = NUM_NB, int num_ic = NUM_IC, int num_oc = NUM_OC> sc_signal<flit> NWTile< num_nb, num_ic, num_oc >::flit_CS_IC

data line from ipcore to input channel

template<int num_nb = NUM_NB, int num_ic = NUM_IC, int num_oc = NUM_OC> sc_signal<flit> NWTile< num_nb, num_ic, num_oc >::flit_OC_CR

data line from output channel to ipcore

template<int num_nb = NUM_NB, int num_ic = NUM_IC, int num_oc = NUM_OC> sc_signal<flit> NWTile< num_nb, num_ic, num_oc >::flit_sig[num_ic][num_oc]

signals to connect data outport of ICs to the data inport of the OCs

template<int num_nb = NUM_NB, int num_ic = NUM_IC, int num_oc = NUM_OC> InputChannel<num_oc>* NWTile< num_nb, num_ic, num_oc >::Ichannel[num_ic]

Input channels.

template<int num_nb = NUM_NB, int num_ic = NUM_IC, int num_oc = NUM_OC> ipcore* NWTile< num_nb, num_ic, num_oc >::ip

IP Core.

template<int num_nb = NUM_NB, int num_ic = NUM_IC, int num_oc = NUM_OC> sc_in<flit> NWTile< num_nb, num_ic, num_oc >::ip_port[num_nb]

input data/flit ports

template<int num_nb = NUM_NB, int num_ic = NUM_IC, int num_oc = NUM_OC> sc_signal<sc_uint<3> > NWTile< num_nb, num_ic, num_oc >::nextRt[num_ic]

Route (output port) signal from Ctr to IC.

template<int num_nb = NUM_NB, int num_ic = NUM_IC, int num_oc = NUM_OC> sc_signal<sc_uint<VCS_BITSIZE+1> > NWTile< num_nb, num_ic, num_oc >::nextvc[num_ic]

Virtual channel id allocated from VCA to IC.

template<int num_nb = NUM_NB, int num_ic = NUM_IC, int num_oc = NUM_OC> OutputChannel<num_ic>* NWTile< num_nb, num_ic, num_oc >::Ochannel[num_oc]

Output channels.

template<int num_nb = NUM_NB, int num_ic = NUM_IC, int num_oc = NUM_OC> sc_out<flit> NWTile< num_nb, num_ic, num_oc >::op_port[num_nb]

output data/flit ports

template<int num_nb = NUM_NB, int num_ic = NUM_IC, int num_oc = NUM_OC> sc_signal<sc_uint<2> > NWTile< num_nb, num_ic, num_oc >::opReq[num_ic]

Output port requested from IC to VCA.

UI BaseNWTile::portE [inherited]

port representing East direction

UI BaseNWTile::portN [inherited]

port representing North direction

UI BaseNWTile::portS [inherited]

port representing South direction

UI BaseNWTile::portW [inherited]

port representing West direction

template<int num_nb = NUM_NB, int num_ic = NUM_IC, int num_oc = NUM_OC> sc_signal<bool> NWTile< num_nb, num_ic, num_oc >::rdy[num_ic][num_oc]

ready signals from ICs to OCs of neighboring tiles

template<int num_nb = NUM_NB, int num_ic = NUM_IC, int num_oc = NUM_OC> sc_signal<bool> NWTile< num_nb, num_ic, num_oc >::rtReady[num_ic]

Ready signal from Ctr to IC.

template<int num_nb = NUM_NB, int num_ic = NUM_IC, int num_oc = NUM_OC> sc_signal<request_type> NWTile< num_nb, num_ic, num_oc >::rtReq[num_ic]

Routing request signal from IC to Ctr.

template<int num_nb = NUM_NB, int num_ic = NUM_IC, int num_oc = NUM_OC> sc_signal<sc_uint<ADDR_SIZE> > NWTile< num_nb, num_ic, num_oc >::srcAddr[num_ic]

Source address from IC to Ctr.

template<int num_nb = NUM_NB, int num_ic = NUM_IC, int num_oc = NUM_OC> sc_in<bool> NWTile< num_nb, num_ic, num_oc >::switch_cntrl

input clock port

UI BaseNWTile::tileID [inherited]

unique tile id

template<int num_nb = NUM_NB, int num_ic = NUM_IC, int num_oc = NUM_OC> VCAllocator<num_ic> NWTile< num_nb, num_ic, num_oc >::vcAlloc

Virtual Channel Allocator.

template<int num_nb = NUM_NB, int num_ic = NUM_IC, int num_oc = NUM_OC> sc_signal<bool> NWTile< num_nb, num_ic, num_oc >::vcReady[num_ic]

Ready signal from VCA to IC.

template<int num_nb = NUM_NB, int num_ic = NUM_IC, int num_oc = NUM_OC> sc_signal<bool> NWTile< num_nb, num_ic, num_oc >::vcReq[num_ic]

Request signal for virtual channel allocation from IC to VCA.

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